ASIC VERIFICATION
We are looking for experienced verification engineers to join the development of low power design and efficient system buses. This individual will be responsible for the unit and cluster level verification of backbone buses and power saving features. In this position, you will be required to create verification infrastructure using latest verification methodologies. You would be expected to understand the design and implementation, define the verification scope, develop the verification infrastructure, test suites and verify the correctness of the design. You will be working with architects, designers, pre- and post-silicon verification teams to accomplish your tasks.
MINIMUM REQUIREMENTS:
• BS / MS with 3-15 years of experience
• Experience in latest ASIC verification methodologies (SV, VMM, MVRC, MVSIM, and Functional Coverage based verification)
• Expertise with verification tools (Verilog or System Verilog or equivalent, VCS or equivalent simulation tools, debug tools like Debussy, GDB)
• Familiarity with ARM bus architecture would be a plus.
• Good debugging and problem solving skills.
• Make, PERL, Shell scripting experience is desirable
• Good communication skills and ability & desire to work as a team player with cross-site teams
Share your profile on shahzad@aasthahs.com
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